![]() EXAMINE aka READ is not available however. They both VERIFY and PROGRAM my device successfully. Tried both 9.1 and 6.1 on my Win7 laptop, and neither one allows the EXAMINE of the Altera MAX EPM7064SLC-44 device I have on my test board. Using this search: I found Quartus 9.1sp2, 9.0sp2, and 6.1 installs. I have seen all the requests for this but have no personal experience doing it. If you can get Intel to offer you an NDA they may get you a deprecated version via private download. Old versions of MaxPlus or Quartus are no longer online for download. The next most recent version of Quartus is then 17.0 and later, up to 22.4 which I think is now the most recent. But reading an existing device is NOT supported in the programmer tool. Full synthesis, programming, and verification. So the earliest version of Quartus now available is 13.0sp1, which supports the MAX7xxxS series among others. Once Intel bought Altera they undid this policy, in typical Intel fashion. As to old software, under Altera they left all the old versions of MaxPlus and Quartus online for download. pof file and the format details are Altera/Intel proprietary). You can't tell what the functionality of the device is by looking at the program image (it is a. Can only be used to reprogram an exact same device. This is a simple program that runs on the Nios II processor, which demonstrates read, write and erase.I am sure you are aware that the software image in the FPGA is just the bits. It’s commonly believed that it’s unhealthy for the flash to write to a byte cell twice without an erase in the middle. Which means a plain write, if the region has been previously erased. Writing can then be done to arbitrary addresses, but effectively the data in the flash is the written data ANDed with the previous content of the memory cells. An erase operation is performed on such 64 kB sector, leaving all its bytes in all-1′s (all bytes are 0xff). The rule is simple: The flash is divided into sectors of 64 kB each. It leaves the user with the responsibility to erase sectors before writing to them. I therefore prefer working with the lowest-level drivers, which merely translate the flash commands into SPI communication. In particular, the higher-level drivers erase flash sectors automatically before writing, which can render some counterintuitive behavior, for example if multiple write requests are made on the same sector. This abstraction is not always necessary, and makes it somewhat difficult to figure out what’s going on (in particular when things go wrong). SoftwareĪltera’s BSP includes drivers for flash operations with multiple layers of abstraction. It’s of course possible to connect the flash to regular I/O pins, but then the FPGA won’t be able to configure from the flash. Note that the flash pin DATA1 is connected to the FPGA pin DATA0 - this is not a mistake, but the correct wiring for AS x 1 interface. Once the configuration is done, these pins become general-purpose I/O (when so required by assignments), which allows regular access to the flash device. The FPGA pins above relate to dual-use of the configuration, which allows the FPGA to configure in Active Serial (AS) x 1 mode. Flash pin DATA1 to epcs_flash_controller_0_data (FPGA pin DATA0).Flash pin nCS to epcs_flash_controller_0_sce (FPGA pin NCSO).Flash pin DCLK to epcs_flash_controller_0_dclk (FPGA pin DCLK).Flash pin DATA0 to epcs_flash_controller_0_sdo (FPGA pin ASDO).The external conduit is connected as follows to an ECPQ flash, for a x1 access: The interrupt signal isn’t used in the software setting given below, but as the connection to the Nios processor, as well as the interrupt number assignment is automatic, let it be.Ĭlock and reset - like the other peripherals. In this example, we’ll assume that the name of Flash Controller in Qsys is epcs_flash_controller_0. The peripheral’s epcs_control_port should be connected to the Nios II’s data master Avalon port (no point connecting it to the instruction master too). In the Qsys project, there should be an instance of the Legacy EPCS/EPCQx1 Flash Controller, configured with the default parameters (not that there is much to configure). A non-OS settings (“bare metal”) setting is assumed.Īnd as a bonus (at the bottom of this post), how to program the flash based upon a SOF file, both with JTAG and by writing directly. This post outlines some technical details on accessing an Altera ECPQ flash from a Nios II processor for read, write and erase. ![]() Posted Under: FPGA, Intel FPGA (Altera) Introduction This post was written by eli on April 23, 2017 ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |